Designing an integrated circuit of a semiconductor chip is a complex process. The chip is usually designed in a hierarchical system by a large group of people with information flowing back and forth. One of the features of designing a chip includes making the contact from the internal circuitry to the outside world. The external contacts are formed using input/output (IO)) pads, which are thick metal pads for facilitating contact. IO pads are typically designed along the periphery of the chip.
However, the IO pads are not directly connected to internal circuitry but through additional circuitry called IO blocks. IO blocks are the interface between internal circuitry such as core logic and the IO pads. Since IO pads are connected with external world, IO blocks need to support various applications and specifications, like impedance matching, slew, jitter. Accordingly, the IO blocks are designed and selected to meet certain minimum performance characteristic. This is required since specific IO blocks are required to, for example, buffer and condition signals in and out of the internal circuitry, provide electrostatic discharge (ESD) protection, electro migration, configuration for design for manufacturing.
The main block of the IO blocks which drives the IO pads is the pad driver block and is known as IO driver. The IO driver comprises of large fingered metal oxide semiconductor field effect transistors (MOSFETs) both n-channel MOSFET (NMOS) and p-channel MOSFET (PMOS), which are designed inside a p-well or an n-well.
The design of such IO drivers has to account for many issues. For example, due to continued scaling of semiconductor devices, the number of transistors in a circuit doubles approximately every 1.5 years facilitated by a corresponding shrink in area of the devices. To enable continued scaling, almost all features in a semiconductor device shrink from one technology generation to the next. The increased functionality of the chip produced by increasing the number of transistors in the chip also increases the number of input/output and power pins per chip. The resulting increase in the number of IO pads increases susceptibility to electrostatic discharge (ESD) and other challenges. This is because ESD events occur through the pins at the interface between the semiconductor chip and the outside world. Therefore, the layout of the IO driver has to be custom designed to protect the internal circuitry from ESD damage.
Electro-migration (EM) is another major phenomenon in the design of IO driver because very large amounts of current is drawn through the IO driver, which may result in breakdown of metal pads and/or lines if special care is not taken while estimating the metal width in designing the IO driver. The metal width controls the current density and therefore the susceptibility of the metal line to electro-migration damage.
However, all the above mentioned effects are layout dependent. Therefore, the layout design of IO driver is difficult and important because it directly impacts chip yield and therefore the total cost.